PMC Sierra Network Card PM5354 User Manual

PM5354  
S/UNI MULTI 2x12  
Released  
Multi-rate SATURN User Network Interface for 2x622 and 4x155  
STS-12c (AU-4-4c) or up to four  
STS-3c (AU-4).  
• Provides support for automatic  
protection switching via a 4-bit LVDS  
777.6 MHz port.  
• Provides cross bar functionality to  
swap STS-12 and STS-3 lines and/or  
clients to/from different APS interfaces.  
• Provides UTOPIA Level 3 32-bit wide  
System Interface (clocked up to 104  
MHz) with parity support for ATM  
applications.  
• Provides SATURN® POS-PHY™  
Level 3 (32-bit System Interface  
(clocked up to 104 MHz) for Packet  
over SONET (POS) or ATM  
applications.  
• Supports independent loop-timed  
operation for each transmit serial  
stream.  
FEATURES  
• Single chip ATM and POS User  
Network Interface that supports up to  
2x622.08 Mbit/s, 4x155.52 Mbit/s,  
1x622.08 + 3x155.52 Mbit/s, or  
2x622.08 Mbit/s + 2x155.52 Mbit/s.  
• Implements the ATM Forum User  
Network Interface Specification and  
the ATM physical layer for Broadband  
ISDN according to CCITT  
• Processes up to four duplex bit-serial  
155.52 Mbit/s STS-3 (STM-1) data  
streams with on-chip clock and data  
recovery and clock synthesis. Each  
STS-3 (STM-1) may contain a single  
STS-3c (AU-4).  
• Permits mixed OC-12 and OC-3 data  
streams.  
• Complies with Telcordia  
GR-253-CORE jitter tolerance, jitter  
transfer, and intrinsic jitter criteria.  
• Provides termination for SONET  
Section, Line, and Path overhead or  
SDH Regenerator Section, Multiplexer  
Section, and High Order Path  
overhead.  
• Provides cross bar functionality to  
swap STS-12 and STS-3 clients  
to/from different line-side interfaces.  
Recommendation I.432.  
• Implements the Point-to-Point Protocol  
(PPP) over SONET/SDH specification  
according to RFC 2615(1619)/1662 of  
the PPP Working Group of the Internet  
Engineering Task Force (IETF).  
• Processes up to two duplex bit-serial  
622.08 Mbit/s STS-12 (STM-4) data  
streams with on-chip clock and data  
recovery and clock synthesis. Each  
STS-12 (STM-4) may contain a single  
BLOCK DIAGRAM  
LINE_IF  
LVDS I/f  
(4)  
SONET/APS  
PL3/UL3  
Transmit  
Section  
Trace  
Processor  
(4)  
Transmit  
Path  
Trace  
Processor  
(4)  
Receive  
APS  
(4)  
STPA  
X-Bar  
TCA/PTPA  
TADR[3:0]  
Transmit Analog  
Circuitry  
TXD_P/N[4:1]  
Transmit  
Regen/  
Multiplexor Container  
Processor  
(4)  
Transmit  
Virtual  
UTOPIA L3/  
POS-PHY  
L3  
Transmit  
Interface  
TENB  
TSX  
Transmit  
Path  
Processor  
(4)  
In  
band  
Alarm  
(4)  
Transmit  
channel  
Assigner  
(4)  
Transmit  
ATM/POS  
processor  
(4)  
Transmit  
Line  
Interface  
Transmit  
X-Bar  
Transmit  
FIFO  
TSOC/TSOP  
PRBS  
generator  
/ monitor  
(4)  
TEOP  
TDAT[31:0]  
Aligner  
(4)  
TPRTY  
TMOD[1:0]  
TERR  
TFCLK  
SARC  
Alarm Report  
Controller (4)  
Clock  
Synthesis  
Unit  
PL3EN  
REFCLK77_P/N  
Bit error  
rate mon  
(4)  
RADR[3:0]  
RENB  
RFCLK  
Receive  
Regen/  
Multiplexor  
Processor  
(4)  
Receive  
UTOPIA L3/  
POS-PHY  
L3  
Receive  
Interface  
Receive  
Path  
Processor  
(4)  
Receive  
channel  
Assigner  
(4)  
Receive  
ATM/POS  
processor  
(4)  
RDAT[31:0]  
Receive  
Line  
Interface  
Virtual  
Container  
Aligner  
(4)  
Receive  
X-Bar  
Receive  
FIFO  
RCA/RVAL  
RPRTY  
RSX  
Receive Analog  
Circuitry  
RXD_P/N[4:1]  
RSOC/RSOP  
REOP  
RMOD[1:0]  
X-Bar  
RERR  
Receive  
Section  
Trace  
Processor Processor  
(4) (4)  
Receive  
Path  
Trace  
Transmit  
APS  
(4)  
SD[4:1]  
Microprocessor  
Interface  
JTAG  
Interface  
SD_TEST  
LVDS I/f  
(4)  
PMC-2021540 (R3)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
© Copyright PMC-Sierra, Inc. 2003  
 

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